Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Process of forming a capacitor with multi-level interconnection technology

Process of forming a capacitor with multi-level interconnection technology

US Patent 6336262 · Granted Jan 8, 2002

Estimated economic value: $17,918,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Shielded semiconductor device structure2013
Method of forming a shielded semiconductor device and structure therefor2012
Thick metal interconnect with metal pad caps at selective sites and process for 2011
Thick metal interconnect with metal pad caps at selective sites and process for 2010
Edge seal for a semiconductor device2007
Stacked via-stud with improved reliability in copper metallurgy2005
Method of making an edge seal for a semiconductor device2004
UV-curable compositions and method of use thereof in microelectronics2004
Multi-level electronic package and method for making same2003
Multi-level electronic package and method for making same2003
Method of forming a lead-free tin-silver-copper based solder alloy on an electro2003
Method of forming a lead-free tin-silver-copper based solder alloy on an electro2003