Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and system for reducing power dissipation in a semiconductor storage device

Method and system for reducing power dissipation in a semiconductor storage device

US Patent 6229750 · Granted May 8, 2001

Estimated economic value: $26,391,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Multi-modal monitoring of links between multiple points2025
Separable, intelligible, single channel voice communication2025
Power efficient voltage level translator circuit2022
Integrated circuit (IC) design methods using engineering change order (ECO) cell2020
Power distribution networks (PDNs) using hybrid grid and pillar arrangements2019
Standard cell architecture for diffusion based on fin count2019
Mitigating length-of-diffusion effect for logic cells and placement thereof2019
Standard cell architecture for diffusion based on fin count2019
Complementary metal oxide semiconductor (CMOS) standard cell circuits employing 2018
Compiler for closed-loop 1×N VLSI design2017
Compiler for closed-loop 1xN VLSI design2014
Compiler for closed-loop 1×N VLSI design2014