Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Test method for high speed memory devices in which limit conditions for the clock are defined

Test method for high speed memory devices in which limit conditions for the clock are defined

US Patent 6201746 · Granted Mar 13, 2001

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Controller for controlling one-time programmable memory, system, and operation m2025
Memory core characteristic screening method and system thereof2025
Memory interface circuitry and built-in self-testing method2024
Composition for preventing or treating autoimmune disease based on LRR domain of2023
Substrate processing apparatus2022
Skin-penetrating peptide and method for using same2020
Quadrature relaxation oscillator using frequency error compensation loop2020
Memory module, memory system including the same, and error correcting method the2019
Memory device, memory controller and operation method thereof2019
Address mapping method of memory system2018
Display apparatus2016
Lead free solder bumps2015