Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Process for fabricating memory cells with two levels of polysilicon for devices of EEPROM type

Process for fabricating memory cells with two levels of polysilicon for devices of EEPROM type

US Patent 5985718 · Granted Nov 16, 1999

Estimated economic value: $21,693,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Process for forming differential spaces in electronics device integrated on a se2011
Method for manufacturing non-volatile memory devices integrated in a semiconduct2008
Method for manufacturing electronic devices having non-volatile memory cells and2003
Method for manufacturing electronic devices having non-volatile memory cells and2003
Mask programmed ROM inviolable by reverse engineering inspections and method of 2003
Method for obtaining a multi-level ROM in an EEPROM process flow2003
Method for obtaining a multi-level ROM in an EEPROM process flow2003
Process for manufacturing electronic devices having non-salicidated non-volatile2003
Process for manufacturing electronic devices having non-salicidated non-volatile2003
Process for producing a semiconductor memory device comprising mass-storage memo2003
Process for producing a semiconductor memory device comprising mass-storage memo2003
Low resistance contact structure for a select transistor of EEPROM memory cells 2003