Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for powering down an integrated circuit having a core that operates at a speed greater than the bus frequency

Method and apparatus for powering down an integrated circuit having a core that operates at a speed greater than the bus frequency

US Patent 5935253 · Granted Aug 10, 1999

Estimated economic value: $109,908,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory array leakage reduction circuit and method2008
Memory array leakage reduction circuit and method2007
Input buffer circuit with dual power down functions2001
Detecting states of signals2001
Reducing timing variance of signals from an electronic device2001
Method and apparatus to monitor a characteristic associated with an electronic d2001
Synchronous interface to a self-timed memory array2000
Integrated circuit having a core which operates at a speed greater than the freq1999
Method and apparatus for powering down an integrated circuit transparently and i1998
Apparatus for operating a microprocessor core and bus controller at a speed grea1997
Method and apparatus for invalidating a cache while in a low power state1997
Zero standby current power-up reset circuit1996