| 7345947 |
Memory array leakage reduction circuit and method |
Jeffrey L. Miller, Mahadevamurty Nemani |
2008-03-18 |
| 7164616 |
Memory array leakage reduction circuit and method |
Jeffrey L. Miller, Mahadevamurty Nemani |
2007-01-16 |
| 6330679 |
Input buffer circuit with dual power down functions |
Vijaya Bandara Wickremarachchi |
2001-12-11 |
| 6298450 |
Detecting states of signals |
Jonathan Liu, Michael J. Allen, David P. DiMarco, Jeffrey L. Miller |
2001-10-02 |
| 6175928 |
Reducing timing variance of signals from an electronic device |
Jonathan Liu, Michael J. Allen, David P. DiMarco, Jeffrey L. Miller |
2001-01-16 |
| 6172546 |
Method and apparatus to monitor a characteristic associated with an electronic device |
Jonathan Liu, Michael J. Allen, David P. DiMarco, Jeffrey L. Miller |
2001-01-09 |
| 6061293 |
Synchronous interface to a self-timed memory array |
Jeffrey L. Miller |
2000-05-09 |
| 5935253 |
Method and apparatus for powering down an integrated circuit having a core that operates at a speed greater than the bus frequency |
John A. Deetz |
1999-08-10 |
| 5884068 |
Integrated circuit having a core which operates at a speed greater than the frequency of the bus |
Robert R. Beutler |
1999-03-16 |
| 5842029 |
Method and apparatus for powering down an integrated circuit transparently and its phase locked loop |
Robert R. Beutler |
1998-11-24 |
| 5634117 |
Apparatus for operating a microprocessor core and bus controller at a speed greater than the speed of a bus clock speed |
Robert R. Beutler |
1997-05-27 |
| 5630146 |
Method and apparatus for invalidating a cache while in a low power state |
Robert R. Beutler |
1997-05-13 |
| 5570050 |
Zero standby current power-up reset circuit |
— |
1996-10-29 |
| 5537581 |
Microprocessor with a core that operates at multiple frequencies |
Robert R. Beutler |
1996-07-16 |
| 5481731 |
Method and apparatus for invalidating a cache while in a low power state |
Robert R. Beutler |
1996-01-02 |