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USPTO Patent Rankings Data through Dec 31, 2025
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James W. Conary — 15 Patents

Intel: 15 patents #2,763 of 30,777Top 9%
Beaverton, OR: #407 of 3,140 inventorsTop 15%
Oregon: #2,909 of 28,073 inventorsTop 15%
Overall (All Time): #307,048 of 4,157,543Top 8%
15 Patents All Time
James W. Conary has been granted 15 US patents while listed as an inventor at Intel. The first was granted in 1996 and the most recent in March 2008. James W. Conary ranks #307,048 of 4,157,543 US inventors in our database (top 7.4%). Patent records list James W. Conary in Beaverton, OR, US.

Issued Patents All Time

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
7345947 Memory array leakage reduction circuit and method Jeffrey L. Miller, Mahadevamurty Nemani 2008-03-18 $17,443,000
7164616 Memory array leakage reduction circuit and method Jeffrey L. Miller, Mahadevamurty Nemani 2007-01-16 $22,781,000
6330679 Input buffer circuit with dual power down functions Vijaya Bandara Wickremarachchi 2001-12-11 $125,527,000
6298450 Detecting states of signals Jonathan Liu, Michael J. Allen, David P. DiMarco, Jeffrey L. Miller 2001-10-02 $98,303,000
6175928 Reducing timing variance of signals from an electronic device Jonathan Liu, Michael J. Allen, David P. DiMarco, Jeffrey L. Miller 2001-01-16 $216,902,000
6172546 Method and apparatus to monitor a characteristic associated with an electronic device Jonathan Liu, Michael J. Allen, David P. DiMarco, Jeffrey L. Miller 2001-01-09 $156,284,000
6061293 Synchronous interface to a self-timed memory array Jeffrey L. Miller 2000-05-09 $498,077,000
5935253 Method and apparatus for powering down an integrated circuit having a core that operates at a speed greater than the bus frequency John A. Deetz 1999-08-10 $109,908,000
5884068 Integrated circuit having a core which operates at a speed greater than the frequency of the bus Robert R. Beutler 1999-03-16 $139,495,000
5842029 Method and apparatus for powering down an integrated circuit transparently and its phase locked loop Robert R. Beutler 1998-11-24 $128,337,000
5634117 Apparatus for operating a microprocessor core and bus controller at a speed greater than the speed of a bus clock speed Robert R. Beutler 1997-05-27 $86,657,000
5630146 Method and apparatus for invalidating a cache while in a low power state Robert R. Beutler 1997-05-13 $68,703,000
5570050 Zero standby current power-up reset circuit 1996-10-29 $142,726,000
5537581 Microprocessor with a core that operates at multiple frequencies Robert R. Beutler 1996-07-16 $31,510,000
5481731 Method and apparatus for invalidating a cache while in a low power state Robert R. Beutler 1996-01-02 $94,165,000