| 6425065 |
Tag RAM with selection module for a variable width address field |
Jeffrey L. Miller |
2002-07-23 |
| 6298450 |
Detecting states of signals |
Jonathan Liu, Michael J. Allen, James W. Conary, Jeffrey L. Miller |
2001-10-02 |
| 6175928 |
Reducing timing variance of signals from an electronic device |
Jonathan Liu, Michael J. Allen, James W. Conary, Jeffrey L. Miller |
2001-01-16 |
| 6172546 |
Method and apparatus to monitor a characteristic associated with an electronic device |
Jonathan Liu, Michael J. Allen, James W. Conary, Jeffrey L. Miller |
2001-01-09 |
| 5644773 |
Sense amplifier timing method and apparatus for peak power reduction |
— |
1997-07-01 |
| 5627991 |
Cache memory having a multiplexor assembly for ordering output on a data chunk basis |
R. Kenneth Hose, Jr., Jeffrey L. Miller |
1997-05-06 |
| 5555529 |
Power saving architecture for a cache memory |
R. Kenneth Hose, Jr. |
1996-09-10 |
| 5436585 |
BiNMOS driver circuit with integrated voltage supply conversion |
— |
1995-07-25 |
| 5422781 |
Sense amplifier timing method and apparatus for peak power production |
— |
1995-06-06 |
| 5373203 |
Decoder and latching circuit with differential outputs |
James W. Nicholes, Douglas D. Smith |
1994-12-13 |
| 5289415 |
Sense amplifier and latching circuit for an SRAM |
James W. Nicholes, Douglas D. Smith |
1994-02-22 |
