Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Reducing cache misses by snarfing writebacks in non-inclusive memory systems

Reducing cache misses by snarfing writebacks in non-inclusive memory systems

US Patent 5909697 · Granted Jun 1, 1999

Estimated economic value: $83,247,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method and apparatus for leveraging simultaneous multithreading for bulk compute2025
Loop support extensions2024
Methods, apparatus, articles of manufacture to perform accelerated matrix multip2022
Sharing resources between a CPU and GPU2019
Single instruction for specifying a subset of registers to save prior to enterin2017
Packet processing architecture2016
Secure memory access controller2016
Extended main memory hierarchy having flash memory for page fault handling2015
Single instruction for specifying and saving a subset of registers, specifying a2015
Shared memory architecture2014
Single instruction for specifying and saving a subset of registers, specifying a2014
Transmission using multiple physical interface2014