Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Parallel calculation of exponent and sticky bit during normalization

Parallel calculation of exponent and sticky bit during normalization

US Patent 5757682 · Granted May 26, 1998

Estimated economic value: $6,589,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Backside self aligned skip via2025
Backside gate via structure using self-aligned scheme2025
Cell optimization through source resistance improvement2025
Single cycle request arbiter2025
Generating a power delivery network based on the routing of signal wires within 2025
Selective mesh routing through non-adjacent nodes2025
Decimal floating-point instruction in a round-for-reround mode2025
Semiconductor device design mitigating latch-up2024
Hierarchical color decomposition of library cells with boundary-aware color sele2024
Region-based power grid generation through modification of an initial power grid2024
Hierarchical color decomposition of process layers with shape and orientation re2023
Prepare for shorter precision (round for reround) mode in a decimal floating-poi2023