Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System and method having processor with selectable burst or no-burst write back mode depending upon signal indicating the system is configured to accept bit width larger than the bus width

System and method having processor with selectable burst or no-burst write back mode depending upon signal indicating the system is configured to accept bit width larger than the bus width

US Patent 5669014 · Granted Sep 16, 1997

Estimated economic value: $105,296,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Increasing power efficiency of turbo mode operation in a processor2014
Efficient frequency boost operation2014
Increasing power efficiency of turbo mode operation in a processor2014
Increasing power efficiency of turbo mode operation in a processor2014
Processor with sleep and deep sleep modes2000
Dynamically sizing a bus transaction for dual bus size interoperability based on2000
Apparatus and method for swapping the byte order of a data item to effectuate me1999
Memory management system including an inclusion bit for maintaining cache cohere1999
Identification of the distinction between the beginning of a new write back cycl1998
Identification of the distinction between the beginning of a new write back cycl1998
LRU pointer updating in a controller for two-way set associative cache1998
Method and apparatus for selecting a mode for updating external memory1997