{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Programmable redundancy scheme suitable for single-bit state and multibit state nonvolatile memories", "item": "https://www.patentleaderboard.com/patent/5438546"}]}

Home › Programmable redundancy scheme suitable for single-bit state and multibit state nonvolatile memories

Programmable redundancy scheme suitable for single-bit state and multibit state nonvolatile memories

US Patent 5438546 · Granted Aug 1, 1995

Estimated economic value: $87,356,000 ⓘ

Assignee

Intel

Inventors

Michel Ibrahim Ishac (4 patents)
Sanjay S. Talreja (25 patents)
Mark E. Bauer (32 patents)

View full patent text on Google Patents →