{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Per-wafer method for globally stressing gate oxide during device fabrication", "item": "https://www.patentleaderboard.com/patent/5391502"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Per-wafer method for globally stressing gate oxide during device fabrication

Per-wafer method for globally stressing gate oxide during device fabrication

US Patent 5391502 · Granted Feb 21, 1995

Estimated economic value: $937,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method for fabricating semiconductor structures on vicinal substrates using a lo2007
Method for preparing a semiconductor substrate surface for semiconductor device 2006
Method and apparatus for optimizing exposure time in image acquisitions2004
Lower temperature method for forming high quality silicon-nitrogen dielectrics2004
Lower temperature method for forming high quality silicon-nitrogen dielectrics2003
Photo-sensor cross-section for increased quantum efficiency2003
Process to produce ultrathin crystalline silicon nitride on Si (111) for advance2002
Process to produce ultrathin crystalline silicon nitride on Si(111) for advanced2001
Lower temperature method for forming high quality silicon-nitrogen dielectrics2001
Method for thin film deposition on single-crystal semiconductor substrates2001
Method of forming a nano-rugged silicon-containing layer2000
High DC current stagger power/ground pad2000