{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Memory address translation system having modifiable and non-modifiable translation mechanisms", "item": "https://www.patentleaderboard.com/patent/5255384"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory address translation system having modifiable and non-modifiable translation mechanisms

Memory address translation system having modifiable and non-modifiable translation mechanisms

US Patent 5255384 · Granted Oct 19, 1993

Estimated economic value: $4,802,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Branch target buffer operation with auxiliary indirect cache2025
System on a chip for networking2011
System on a chip for networking2010
System on a chip for networking2008
Circuit group design methodologies2007
System for repair of ROM programming errors or defects2006
Bus sampling on one edge of a clock signal and driving on another edge2006
Bus precharge during a phase of a clock signal to eliminate idle clock cycle2006
Idle power reduction for state machines2006
Instruction cache association crossbar switch2006
Circuit group design methodologies2005
VLIW processor and method therefor2005