Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer

Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer

US Patent 5113515 · Granted May 12, 1992

Estimated economic value: $9,745,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Systems, methods, and apparatuses for heterogeneous computing2024
Systems, methods, and apparatuses for heterogeneous computing2023
Systems, methods, and apparatuses for heterogeneous computing2022
Systems, methods, and apparatuses for heterogeneous computing2021
Extended main memory hierarchy having flash memory for page fault handling2015
Cache coherent support for flash in a memory hierarchy2012
Multiple-core processor with support for multiple virtual processors2011
Multiple-core, multithreaded processor with flexible error steering mechanism2010
Multiple-core processor with flexible mapping of processor cores to cache banks2010
System interface unit2010
ECC encoding for uncorrectable errors2009
Use of FBDIMM channel as memory channel and coherence channel2009