Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for addressing a cache memory

Method and apparatus for addressing a cache memory

US Patent 4884197 · Granted Nov 28, 1989

Estimated economic value: $7,679,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Branch target buffer operation with auxiliary indirect cache2025
System on a chip for networking2011
System on a chip for networking2010
System on a chip for networking2008
Circuit group design methodologies2007
System for repair of ROM programming errors or defects2006
Bus sampling on one edge of a clock signal and driving on another edge2006
Bus precharge during a phase of a clock signal to eliminate idle clock cycle2006
Idle power reduction for state machines2006
Instruction cache association crossbar switch2006
Circuit group design methodologies2005
VLIW processor and method therefor2005