Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Random instruction-side stressing in post-silicon validation

Random instruction-side stressing in post-silicon validation

US Patent 12353307 · Granted Jul 8, 2025

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Detecting hardware errors2025
Random function selection and insertion during compilation for post-silicon vali2025
Validating address space context switches by loading an alternative address spac2024
Validating address space context switches by loading an alternative address spac2024
Test space sampling for model-based biased random system test through rest API2024
Testing of hardware queue systems using on device test generation2024
Testing of hardware queue systems using on device test generation2024
Compiler-based code generation for post-silicon validation2023
Compiler-based code generation for post-silicon validation2023
Model-based biased random system test through rest API2023
Testing address translation cache2022
Testing address translation cache2022