| 12353307 |
Random instruction-side stressing in post-silicon validation |
Tom Kolan |
2025-07-08 |
| 12203986 |
Random function selection and insertion during compilation for post-silicon validation |
Idan Horowitz, Karen Holtz, Dani Szebenyi, Ido Plat |
2025-01-21 |
| 12174750 |
Validating address space context switches by loading an alternative address space from an address translation independent location |
Idan Horowitz, Tom Kolan, Eliran Roffe |
2024-12-24 |
| 11907088 |
Testing of hardware queue systems using on device test generation |
Tom Kolan, Hagai Hadad, Shay Aviv |
2024-02-20 |
| 11796593 |
Compiler-based code generation for post-silicon validation |
Tom Kolan, Shay Aviv, Vitali Sokhin, Wesam Saleem Ibraheem |
2023-10-24 |
| 11263150 |
Testing address translation cache |
Tom Kolan, Vitali Sokhin |
2022-03-01 |
| 11226370 |
Recoverable exceptions generation and handling for post-silicon validation |
Vitali Sokhin, Tom Kolan, Hernan Theiler, Shai Doron |
2022-01-18 |
| 11204859 |
Partial-results post-silicon hardware exerciser |
Tom Kolan, Alex Lvovsky, Vitali Sokhin |
2021-12-21 |
| 11200126 |
Utilizing translation tables for testing processors |
Tom Kolan, Vitali Sokhin, Shay Aviv |
2021-12-14 |
| 11194705 |
Automatically introducing register dependencies to tests |
Tom Kolan, Vitali Sokhin |
2021-12-07 |
| 11182265 |
Method and apparatus for test generation |
Tom Kolan, Vitali Sokhin |
2021-11-23 |
| 10496449 |
Verification of atomic memory operations |
Tom Kolan, Vitali Sokhin |
2019-12-03 |
