Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Aliased mode for cache controller

Aliased mode for cache controller

US Patent 12086064 · Granted Sep 10, 2024

Estimated economic value: $30,309,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Pipelined read-modify-write operations in cache memory2025
Register file structures combining vector and scalar data with global and local 2025
Write control for read-modify-write operations in cache memory2025
Write control for read-modify-write operations in cache memory2025
Vector maximum and minimum with indexing2025
Method and apparatus for implied bit handling in floating point multiplication2025
Controller with caching and non-caching modes2025
Controller with caching and non-caching modes2025
System and method to control the number of active vector lanes in a processor2025
Victim cache that supports draining write-miss entries2025
Victim cache that supports draining write-miss entries2025
System and method for predication handling2025