Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Managing sub-block erase operations in a memory sub-system

Managing sub-block erase operations in a memory sub-system

US Patent 12068037 · Granted Aug 20, 2024

Estimated economic value: $25,472,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Fast bit erase for upper tail tightening of threshold voltage distributions2025
Volatile data storage in NAND memory2025
Dynamic latches above a three-dimensional non-volatile memory array2025
Double single level cell program in a memory device2025
Establishing bitline, wordline and boost voltages to manage a maximum program vo2025
Single-level cell program-verify, latch-limited data recovery2025
Memory devices with controlled wordline ramp rates, and associated systems and m2025
Rating-based mapping of data to memory2025
Apparatus for determination of capacitive and resistive characteristics of acces2025
Creating dynamic latches above a three-dimensional non-volatile memory array2025
In-line programming adjustment of a memory cell in a memory sub-system2025
Systems and machine learning models for automated vehicle monitoring2025