Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Chip-scale package architectures containing a die back side metal and a solder thermal interface material

Chip-scale package architectures containing a die back side metal and a solder thermal interface material

US Patent 12040246 · Granted Jul 16, 2024

Estimated economic value: $26,089,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

BGA stiffener attachment with low Eolife adhesive strength at high solder joint 2025
Ultra-thin, hyper-density semiconductor packages2025
Nested glass packaging architecture for hybrid electrical and optical communicat2025
Ultra-thin, hyper-density semiconductor packages2025
Photonic integrated circuit packaging architectures2025
Mold shelf package design and process flow for advanced package architectures2025
Integrated circuit die package stiffeners of metal alloys having exceptionally h2024
Integrated circuit die package stiffeners of metal alloys having exceptionally h2024
Open cavity bridge co-planar placement architectures and processes2024
Solder thermal interface material (STIM) with dopant2024
No mold shelf package design and process flow for advanced package architectures2024
Dummy die structures of a packaged integrated circuit device2024