Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System and method for conducting built-in self-test of memory macro

System and method for conducting built-in self-test of memory macro

US Patent 12033710 · Granted Jul 9, 2024

Estimated economic value: $15,647,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Scan synchronous-write-through testing architectures for a memory device2025
Conducting built-in self-test of memory macro2025
Conducting built-in self-test of memory macro2025
Conducting built-in self-test of memory macro2025
Scan architecture for interconnect testing in 3D integrated circuits2025
Scan architecture for interconnect testing in 3D integrated circuits2025
Authentication based on physically unclonable functions2025
Physical unclonable function (PUF) security key generation2025
PUF method and structure2024
Memory address protection circuit including an error detection circuit and metho2024
Gradated service access based on identity verification (IDV)2024
Scan architecture for interconnect testing in 3D integrated circuits2024