Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Branch target buffer that stores predicted set index and predicted way number of instruction cache

Branch target buffer that stores predicted set index and predicted way number of instruction cache

US Patent 12008375 · Granted Jun 11, 2024

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Microprocessor that builds consistent loop iteration count unrolled loop multi-f2025
Microprocessor that allows same-fetch block start address co-residence of unroll2025
Microprocessor that builds multi-fetch block macro-op cache entries in two-stage2025
Microprocessor that performs partial fallback abort processing of multi-fetch bl2025
Prediction unit that predicts successor fetch block start address of multi-fetch2025
Physical address proxy (PAP) residency determination for reduction of PAP reuse2025
Microprocessor that builds inconsistent loop that iteration count unrolled loop 2025
Microprocessor that performs mid-macro-op cache entry restart abort processing2025
Microprocessor that extends sequential multi-fetch block macro-op cache entries2025
Using physical address proxies to accomplish penalty-less processing of load/sto2025
Prediction unit with first predictor that provides a hashed fetch address of a c2025
Prediction unit that predicts branch history update information produced by mult2025