Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Microprocessor that builds multi-fetch block macro-op cache entries in two-stage process

Microprocessor that builds multi-fetch block macro-op cache entries in two-stage process

US Patent 12498928 · Granted Dec 16, 2025

Assignee

No assignee recorded.

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Microprocessor that builds consistent loop iteration count unrolled loop multi-f2025
Microprocessor that builds consistent loop iteration count unrolled loop multi-f2025
Microprocessor that allows same-fetch block start address co-residence of unroll2025
Microprocessor that allows same-fetch block start address co-residence of unroll2025
Microprocessor that performs partial fallback abort processing of multi-fetch bl2025
Microprocessor that performs partial fallback abort processing of multi-fetch bl2025
Prediction unit that predicts successor fetch block start address of multi-fetch2025
Prediction unit that predicts successor fetch block start address of multi-fetch2025
Physical address proxy (PAP) residency determination for reduction of PAP reuse2025
Microprocessor that builds inconsistent loop that iteration count unrolled loop 2025
Microprocessor that builds inconsistent loop that iteration count unrolled loop 2025
Microprocessor that performs mid-macro-op cache entry restart abort processing2025