Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Layout techniques and optimization for power transistors

Layout techniques and optimization for power transistors

US Patent 11929408 · Granted Mar 12, 2024

Estimated economic value: $15,448,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Layout techniques and optimization for power transistors2025
Layout techniques and optimization for power transistors2025
Layout techniques and optimization for power transistors2025
Layout techniques and optimization for power transistors2025
Layout techniques and optimization for power transistors2025
Circuit and method of shutdown for bias network in high voltage amplifier2025
Parasitic capacitance reduction in GaN-on-silicon devices2025
Extrinsic field termination structures for improving reliability of high-voltage2025
Atomic layer deposition of barrier metal layer for electrode of gallium nitride 2024
High voltage stacked transistor amplifier2024
High voltage stacked transistor amplifier2024
Methods and systems for ground recover in a transducer array2024