Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Layout techniques and optimization for power transistors

Layout techniques and optimization for power transistors

US Patent 12363983 · Granted Jul 15, 2025

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Circuit and method of shutdown for bias network in high voltage amplifier2025
Parasitic capacitance reduction in GaN-on-silicon devices2025
Extrinsic field termination structures for improving reliability of high-voltage2025
Atomic layer deposition of barrier metal layer for electrode of gallium nitride 2024
High voltage stacked transistor amplifier2024
High voltage stacked transistor amplifier2024
Methods and systems for ground recover in a transducer array2024
Methods and systems for a multi-frequency transducer array2024
Gate metal formation on gallium nitride or aluminum gallium nitride2024
Gate metal formation on gallium nitride or aluminum gallium nitride2024
Gate metal formation on gallium nitride or aluminum gallium nitride2024
Extrinsic field termination structures for improving reliability of high-voltage2024