Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array

Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array

US Patent 11910612 · Granted Feb 20, 2024

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Methods for fabricating a 3-dimensional memory structure of nor memory strings2025
Thin film storage transistor with silicon oxide nitride charge trapping layer2025
Wound healing analysis and tracking2025
Bearing monitoring/analysis system2025
High capacity memory circuit with low effective latency2025
High capacity memory circuit with low effective latency2025
Micro flow measuring device and method based on mass method2025
Determining offsets for memory read operations2025
Device with embedded high-bandwidth, high-capacity memory using wafer bonding2025
Device with embedded high-bandwidth, high-capacity memory using wafer bonding2025
Three-dimensional memory string array of thin-film ferroelectric transistors for2025
Three-dimensional memory string array of thin-film ferroelectric transistors for2025