Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Integration of p-channel and n-channel E-FET III-V devices with optimization of device performance

Integration of p-channel and n-channel E-FET III-V devices with optimization of device performance

US Patent 11824109 · Granted Nov 21, 2023

Estimated economic value: $8,803,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Two-section head mounted system2025
Barrier structure configured to increase performance of III-V devices2025
Barrier structure configured to increase performance of III-V devices2025
3D IC comprising semiconductor substrates with different bandgaps2025
Cap structure coupled to source to reduce saturation current in HEMT device2025
Ring transistor structure2025
Ring transistor structure2025
Source leakage current suppression by source surrounding gate structure2025
Source leakage current suppression by source surrounding gate structure2025
Integration of p-channel and n-channel E-FET III-V devices with optimization of 2025
Integration of p-channel and n-channel E-FET III-V devices with optimization of 2025
Integration of p-channel and n-channel E-FET III-V devices with optimization of 2025