Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Interconnect integration scheme with fully self-aligned vias

Interconnect integration scheme with fully self-aligned vias

US Patent 11264276 · Granted Mar 1, 2022

Estimated economic value: $6,542,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Magnetoresistive random-access memory (MRAM) with preserved underlying dielectri2025
Magnetoresistive random-access memory (MRAM) with preserved underlying dielectri2025
Rework for metal interconnects using etch and thermal anneal2024
Contacts having a geometry to reduce resistance2024
Interconnect structures including self aligned vias2023
Interconnect structures including self aligned vias2023
Multiple patterning with mandrel cuts defined by block masks2022
Metal on metal multiple patterning2022
Double patterning interconnect integration scheme with SAV2022
Double patterning interconnect integration scheme with SAV2022
Embedded BEOL memory device with top electrode pillar2022
Interconnect structures including self aligned vias2022