Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Leveraging low power states for fault testing of processing cores at runtime

Leveraging low power states for fault testing of processing cores at runtime

US Patent 11204849 · Granted Dec 21, 2021

Estimated economic value: $3,325,835,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Technique for enabling on-die noise measurement during ate testing and IST2025
Test data transfer in multi-die systems2025
Generalized acceleration of matrix multiply accumulate operations2025
Techniques to power balance multiple chips2025
Asynchronous in-system testing for autonomous systems and applications2025
Performing diagnostic operations on a target system2025
System for automated data retrieval from an integrated circuit for event analysi2025
Leveraging low power states for fault testing of processing cores at runtime2024
Leveraging low power states for fault testing of processing cores at runtime2024
Leveraging low power states for fault testing of processing cores at runtime2024
Leveraging low power states for fault testing of processing cores at runtime2024
In system test of chips in functional systems2024