Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Device structure for a 3-dimensional NOR memory array and methods for improved erase operations applied thereto

Device structure for a 3-dimensional NOR memory array and methods for improved erase operations applied thereto

US Patent 11069696 · Granted Jul 20, 2021

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Methods for reducing disturb errors by refreshing data alongside programming or 2025
Methods for fabricating a 3-dimensional memory structure of nor memory strings2025
High capacity memory circuit with low effective latency2025
Device with embedded high-bandwidth, high-capacity memory using wafer bonding2025
Three-dimensional memory string array of thin-film ferroelectric transistors for2025
Three-dimensional memory string array of thin-film ferroelectric transistors for2025
Vertical thin-film transistor and application as bit-line connector for 3-dimens2025
Vertical thin-film transistor and application as bit-line connector for 3-dimens2025
Multi-gate nor flash thin-film transistor strings arranged in stacked horizontal2025
Methods for forming multilayer horizontal NOR-type thin-film memory strings2025
Methods for forming multilayer horizontal NOR-type thin-film memory strings2025
Silicon oxide nitride tunnel dielectric for a storage transistor in a 3-dimensio2025