Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Closely packed vertical transistors with reduced contact resistance

Closely packed vertical transistors with reduced contact resistance

US Patent 11011622 · Granted May 18, 2021

Estimated economic value: $4,116,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Vertically stacked FET with strained channel2025
Vertically stacked FET with strained channel2025
Nanowire source/drain formation for nanosheet device2025
Strain generation and anchoring in gate-all-around field effect transistors2025
Buried power rail with robust connection to a wrap around contact2025
Semiconductor structure with wrapped-around backside contact2025
Fuel rod having heat transfer liquid filling the gap between fuel pellets and cl2025
Two-dimensional vertical fins2025
Gain cell memory based physically unclonable function2025
Stressed material within gate cut region2025
Air gap spacer for metal gates2025
Stacked cross-point phase change memory2025