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Home › Circuits employing adjacent low-k dummy gate to a field-effect transistor (FET) to reduce FET source/drain parasitic capacitance, and related fabrication methods

Circuits employing adjacent low-k dummy gate to a field-effect transistor (FET) to reduce FET source/drain parasitic capacitance, and related fabrication methods

US Patent 11011602 · Granted May 18, 2021

Estimated economic value: $30,492,000 ⓘ

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