Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Implementation of execution compression of instructions in slice target register file mapper

Implementation of execution compression of instructions in slice target register file mapper

US Patent 10949205 · Granted Mar 16, 2021

Estimated economic value: $6,230,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Systolic array with input reduction to multiple reduced inputs2025
Data-type-aware clock-gating2025
Systems and methods for dynamic control of a secure mode of operation in a proce2025
Routing instructions in a microprocessor2025
Routing instruction results to a register block of a subdivided register file ba2025
Routing instruction results to a register block of a subdivided register file ba2025
Increasing performance of computational array accelerators2024
Parallel slice processor having a recirculating load-store queue for fast deallo2024
Parallel slice processor having a recirculating load-store queue for fast deallo2024
Parallel slice processor having a recirculating load-store queue for fast deallo2024
Dispatching multiply and accumulate operations based on accumulator register ind2024
Method and system for on demand control of hardware support for software pointer2024