{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Method for copper plating through silicon vias using wet wafer back contact", "item": "https://www.patentleaderboard.com/patent/10879116"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for copper plating through silicon vias using wet wafer back contact

Method for copper plating through silicon vias using wet wafer back contact

US Patent 10879116 · Granted Dec 29, 2020

Estimated economic value: $47,583,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Semiconductor device packages2025
High connectivity device stacking2025
Package core assembly and fabrication methods2025
Package core assembly and fabrication methods2025
Method and apparatus for laser drilling blind vias2025
Method and apparatus for laser drilling blind vias2025
Reconstituted substrate structure and fabrication methods for heterogeneous pack2025
Package core assembly and fabrication methods2024
Package core assembly and fabrication methods2024
Planarization methods for packaging substrates2024
Fluoropolymer stamp fabrication method2024
Fluoropolymer stamp fabrication method2024