Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Selective inclusion/exclusion of semiconductor chips in accelerated failure tests

Selective inclusion/exclusion of semiconductor chips in accelerated failure tests

US Patent 10777470 · Granted Sep 15, 2020

Estimated economic value: $3,826,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Multi-machine learning system for interacting with a large language model2025
Identification of hot spots or defects by machine learning2025
Customizable framework for natural language processing explainability2025
Wafer bin map based root cause analysis2025
Wafer bin map based root cause analysis2025
Wafer bin map based root cause analysis2025
Machine learning variable selection and root cause discovery by cumulative predi2025
Converting natural language queries to SQL queries using ontological codes and p2024
Collaborative learning model for semiconductor applications2024
Collaborative learning model for semiconductor applications2024
Collaborative learning model for semiconductor applications2024
Abnormal wafer image classification2024