Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Verification complexity reduction via range-preserving input-to-constant conversion

Verification complexity reduction via range-preserving input-to-constant conversion

US Patent 10540468 · Granted Jan 21, 2020

Estimated economic value: $2,593,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Equivalence checking of synthesized logic designs using generated synthesis hist2025
Equivalence checking of synthesized logic designs using generated synthesis hist2025
Equivalence checking of synthesized logic designs using generated synthesis hist2025
Co-debug of processing conditions of logic devices2025
Optimization of arithmetic expressions2024
Optimization of arithmetic expressions2024
Detection of unintended dependencies in hardware designs with pseudo-random numb2023
Hardware verification based on relations between coverage events2021
Scalable connectivity verification using conditional cut-points2021
Scalable connectivity verification using conditional cut-points2021
Scalable connectivity verification using conditional cut-points2021
Grouping and partitioning of properties for logic verification2020