Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Hitless switching when generating an output clock derived from multiple redundant input clocks

Hitless switching when generating an output clock derived from multiple redundant input clocks

US Patent 10514720 · Granted Dec 24, 2019

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Inter-PLL communication in a multi-PLL environment2025
Inter-PLL communication in a multi-PLL environment2025
Inter-PLL communication in a multi-PLL environment2025
Counter design for a time-to-digital converter (TDC)2025
Generating divided signals from phase-locked loop (PLL) output when reference cl2024
Generating divided signals from phase-locked loop (PLL) output when reference cl2024
Generating divided signals from phase-locked loop (PLL) output when reference cl2024
Preventing reverse-current flow when an integrated circuit operates using power 2024
Preventing reverse-current flow when an integrated circuit operates using power 2024
Generating divided signals from phase-locked loop (PLL) output when reference cl2024
Generating divided signals from phase-locked loop (PLL) output when reference cl2024
Generating divided signals from phase-locked loop (PLL) output when reference cl2024