Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses

Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses

US Patent 10417002 · Granted Sep 17, 2019

Estimated economic value: $3,647,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Gather buffer management for unaligned and gather load operations2025
Pseudo lock-step execution across CPU cores2025
Dependency skipping in a load-compare-jump sequence of instructions by incorpora2024
Inferring future value for speculative branch resolution in a microprocessor2024
Prioritization of threads in a simultaneous multithreading processor core2023
Gather buffer management for unaligned and gather load operations2023
Microprocessor that fuses load and compare instructions2023
Inferring future value for speculative branch resolution2023
Processor overriding of a false load-hit-store detection2023
Dependency skipping execution2023
Virtual cache synonym detection using alias tags2023
Translation bandwidth optimized prefetching strategy through multiple translatio2023