Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Capping poly channel pillars in stacked circuits

Capping poly channel pillars in stacked circuits

US Patent 10319678 · Granted Jun 11, 2019

Estimated economic value: $16,707,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method for manufacturing a memory structure having stacked data lines and conduc2025
Optical probe with high stability for measurement of radiation information of tu2025
Stack of horizontally extending and vertically overlapping features, methods of 2025
Electronic devices including support pillars in slot regions, and related memory2025
Microelectronic devices and related memory devices2025
Tracking instruction handling using opcode matching in processor-based devices2025
On-pitch vias for semiconductor devices and associated devices and systems2025
Methods of exposing conductive Vias of semiconductor devices and related semicon2025
Memory device including multiple decks of memory cells and pillars extending thr2024
Multitier arrangements of integrated devices, and methods of forming sense/acces2024
Three dimensional memory2024
Methods of forming microelectronic devices2024