Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Timing analysis and optimization of asynchronous circuit designs

Timing analysis and optimization of asynchronous circuit designs

US Patent 10318691 · Granted Jun 11, 2019

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Alignment cost for integrated circuit placement2025
Generating integrated circuit placements using neural networks2025
Generating integrated circuit placements using neural networks2023
Generating integrated circuit placements using neural networks2023
Generating integrated circuit placements using neural networks2022
Method for repeated block modification for chip routing2014
Method for repeated block modification for chip routing2014
Method for repeated block modification for chip routing2013
Method for repeated block modification for chip routing2013
Method for repeated block timing analysis2011
Regulator for pumped voltage generator1996
Structure and method for testing wiring segments in an integrated circuit device1996