Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Transistor die with drain via arrangement, and methods of manufacture thereof

Transistor die with drain via arrangement, and methods of manufacture thereof

US Patent 10103233 · Granted Oct 16, 2018

Estimated economic value: $9,974,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Wafer with semiconductor devices and integrated electrostatic discharge protecti2025
Transistors with self-aligned source-connected field plates2025
Semiconductor device with conductive elements formed over dielectric layers and 2025
Transistor die with primary and ancillary transistor elements2025
Semiconductor device with an insulating region formed between a control electrod2025
Power amplifier with a power transistor and an electrostatic discharge protectio2024
Transistor with integrated passive components2024
LDMOS transistor with implant alignment spacers2024
T-match topology with baseband termination2024
Transistor circuits with shielded reference transistors2024
Semiconductor device with conductive elements formed over dielectric layers and 2024
Amplifier modules and systems with ground terminals adjacent to power amplifier 2023