Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6614258 | Field-programmable dynamic logic array | — | 2003-09-02 |
| 6542958 | Software control of DRAM refresh to reduce power consumption in a data processing system | — | 2003-04-01 |
| 6502202 | Self-adjusting multi-speed pipeline | — | 2002-12-31 |
| 6433581 | Configurable dynamic programmable logic array | — | 2002-08-13 |
| 6348812 | Dynamic programmable logic array that can be reprogrammed and a method of use | — | 2002-02-19 |
| 6304102 | Repairable dynamic programmable logic array | — | 2001-10-16 |
| 6094705 | Method and system for selective DRAM refresh to reduce power consumption | — | 2000-07-25 |
| 6061711 | Efficient context saving and restoring in a multi-tasking computing system environment | Moataz A. Mohamed, Heonchul Park, Le Trong Nguyen, Jerry R. Van Aken, Alessandro Forin +1 more | 2000-05-09 |
| 6041167 | Method and system for reordering instructions after dispatch in a processing system | — | 2000-03-21 |
| 5991531 | Scalable width vector processor architecture for efficient emulation | Heonchul Park | 1999-11-23 |
| 5922066 | Multifunction data aligner in wide data width processor | Seongrai Cho, Heonchul Park | 1999-07-13 |
| 5893930 | Predictive translation of a data address utilizing sets of associative entries stored consecutively in a translation lookaside buffer | — | 1999-04-13 |
| 5881307 | Deferred store data read with simple anti-dependency pipeline inter-lock control in superscalar processor | Heonchul Park | 1999-03-09 |
| 5838984 | Single-instruction-multiple-data processing using multiple banks of vector registers | Le Trong Nguyen, Moataz A. Mohamed, Heonchul Park, Roney S. Wong | 1998-11-17 |
| 5805877 | Data processor with branch target address cache and method of operation | Bryan Black, Marvin Denman | 1998-09-08 |
| 5799163 | Opportunistic operand forwarding to minimize register file read ports | Heonchul Park | 1998-08-25 |
| 5761723 | Data processor with branch prediction and method of operation | Bryan Black, Marvin Denman, Mark A. Kearney | 1998-06-02 |
| 5742802 | Method and system for efficiently mapping guest instruction in an emulation assist unit | Ronald Harter, Gary D. Huber, Arturo Martin-de-Nicolas | 1998-04-21 |
| 5664215 | Data processor with an execution unit for performing load instructions and method of operation | David P. Burgess, Marvin Denman, Milton M. Hood, Jr., Mark A. Kearney, Lavanya Kling +1 more | 1997-09-02 |
| 5644779 | Processing system and method of operation for concurrent processing of branch instructions with cancelling of processing of a branch instruction | — | 1997-07-01 |
| 5559976 | System for instruction completion independent of result write-back responsive to both exception free completion of execution and completion of all logically prior instructions | — | 1996-09-24 |
| 5548738 | System and method for processing an instruction in a processing system | — | 1996-08-20 |
| 5546599 | Processing system and method of operation for processing dispatched instructions with detected exceptions | — | 1996-08-13 |
| 5524224 | System for speculatively executing instructions wherein mispredicted instruction is executed prior to completion of branch processing | Marvin Denman, Artie Pennington | 1996-06-04 |
| 5321825 | Processing system with lock spaces for providing critical section access | — | 1994-06-14 |