Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10118200 | System and method for binning at final test | Reed Linde | 2018-11-06 |
| 9529036 | Systems and methods for test time outlier detection and correction in integrated circuit testing | Reed Linde, Avi Golan | 2016-12-27 |
| 8872538 | Systems and methods for test time outlier detection and correction in integrated circuit testing | Reed Linde, Avi Golan | 2014-10-28 |
| 8781773 | System and methods for parametric testing | Leonid Gurov, Alexander Chufarovsky, Reed Linde | 2014-07-15 |
| 8421494 | Systems and methods for test time outlier detection and correction in integrated circuit testing | Reed Linde, Avi Golan | 2013-04-16 |
| 8112249 | System and methods for parametric test time reduction | Leonid Gurov, Alexander Chufarovsky | 2012-02-07 |
| 8069130 | Methods and systems for semiconductor testing using a testing scenario language | — | 2011-11-29 |
| 7969174 | Systems and methods for test time outlier detection and correction in integrated circuit testing | Reed Linde, Avi Golan | 2011-06-28 |
| 7777515 | Methods and systems for semiconductor testing using reference dice | — | 2010-08-17 |
| 7737716 | Methods and systems for semiconductor testing using reference dice | — | 2010-06-15 |
| 7679392 | Methods and systems for semiconductor testing using reference dice | — | 2010-03-16 |
| 7567947 | Methods and systems for semiconductor testing using a testing scenario language | — | 2009-07-28 |
| 7532024 | Methods and systems for semiconductor testing using reference dice | — | 2009-05-12 |
| 7528622 | Methods for slow test time detection of an integrated circuit during parallel testing | Reed Linde, Avi Golan | 2009-05-05 |
| 7340359 | Augmenting semiconductor's devices quality and reliability | Nir Erez | 2008-03-04 |