Reed Linde — 12 Patents at Optimal Plus

Reed Linde has been granted 12 US patents while listed as an inventor at Optimal Plus. The first was granted in 2007 and the most recent in March 2024. Reed Linde ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list Reed Linde in Cameron Park, CA, US.

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Showing 1–12 of 12 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
11919046	System and method for binning at final test	Gill Balog	2024-03-05
11235355	System and method for binning at final test	Gill Balog	2022-02-01
10118200	System and method for binning at final test	Gil Balog	2018-11-06
9529036	Systems and methods for test time outlier detection and correction in integrated circuit testing	Gil Balog, Avi Golan	2016-12-27
8872538	Systems and methods for test time outlier detection and correction in integrated circuit testing	Gil Balog, Avi Golan	2014-10-28
8838408	Misalignment indication decision system and method	Dan GLOTTER, Alexander Chufarovsky, Leonid Gurov	2014-09-16
8781773	System and methods for parametric testing	Leonid Gurov, Alexander Chufarovsky, Gil Balog	2014-07-15
8421494	Systems and methods for test time outlier detection and correction in integrated circuit testing	Gil Balog, Avi Golan	2013-04-16
7969174	Systems and methods for test time outlier detection and correction in integrated circuit testing	Gil Balog, Avi Golan	2011-06-28
7528622	Methods for slow test time detection of an integrated circuit during parallel testing	Gil Balog, Avi Golan	2009-05-05
7405586	Ultra low pin count interface for die testing	Sunil Gupta, Rich Fackenthal	2008-07-29	$26,149,000
7177189	Memory defect detection and self-repair technique	Alec W. Smidt	2007-02-13	$12,105,000

Reed Linde — 12 Patents

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