Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11919046 | System and method for binning at final test | Gill Balog | 2024-03-05 |
| 11235355 | System and method for binning at final test | Gill Balog | 2022-02-01 |
| 10118200 | System and method for binning at final test | Gil Balog | 2018-11-06 |
| 9529036 | Systems and methods for test time outlier detection and correction in integrated circuit testing | Gil Balog, Avi Golan | 2016-12-27 |
| 8872538 | Systems and methods for test time outlier detection and correction in integrated circuit testing | Gil Balog, Avi Golan | 2014-10-28 |
| 8838408 | Misalignment indication decision system and method | Dan GLOTTER, Alexander Chufarovsky, Leonid Gurov | 2014-09-16 |
| 8781773 | System and methods for parametric testing | Leonid Gurov, Alexander Chufarovsky, Gil Balog | 2014-07-15 |
| 8421494 | Systems and methods for test time outlier detection and correction in integrated circuit testing | Gil Balog, Avi Golan | 2013-04-16 |
| 7969174 | Systems and methods for test time outlier detection and correction in integrated circuit testing | Gil Balog, Avi Golan | 2011-06-28 |
| 7528622 | Methods for slow test time detection of an integrated circuit during parallel testing | Gil Balog, Avi Golan | 2009-05-05 |
| 7405586 | Ultra low pin count interface for die testing | Sunil Gupta, Rich Fackenthal | 2008-07-29 |
| 7177189 | Memory defect detection and self-repair technique | Alec W. Smidt | 2007-02-13 |