SP

Scott Pitkethly

NV NVIDIA: 6 patents #1,173 of 7,811Top 20%
TR Transmeta: 3 patents #29 of 86Top 35%
IN Intel: 2 patents #13,213 of 30,777Top 45%
HP HP: 1 patents #3,612 of 7,018Top 55%
Overall (All Time): #192,341 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12072815 Techniques for data bus inversion with improved latency Anurag Chaudhary, Peter Gentle 2024-08-27
9911470 Fast-bypass memory circuit Venkata Kottapalli, Christian Klingner, Matthew P. Gerlach 2018-03-06
9595968 Cross point switch Robert P. Masleid 2017-03-14
9569214 Execution pipeline data forwarding Gokul Govindu, Parag Gupta, Guillermo J. Rozas 2017-02-14
9178505 Cross point switch Robert P. Masleid 2015-11-03
8848458 Fast-bypass memory circuit Venkata Kottapalli, Christian Klingner, Matthew P. Gerlach 2014-09-30
8838665 Fast condition code generation for arithmetic logic unit 2014-09-16
8762444 Fast condition code generation for arithmetic logic unit Peter Gentle 2014-06-24
8451025 Advanced repeater with duty cycle adjustment 2013-05-28
8022731 Advanced repeater with duty cycle adjustment 2011-09-20
7872492 Triple latch flip flop system and method Robert P. Masleid 2011-01-18
7768295 Advanced repeater utilizing signal distribution delay Robert P. Masleid 2010-08-03
7730440 Clock signal distribution system and method 2010-06-01
7710153 Cross point switch Robert P. Masleid 2010-05-04
7705633 Advanced repeater with duty cycle adjustment 2010-04-27
7689963 Double diamond clock and power distribution Robert P. Masleid 2010-03-30
7661086 Enhanced clock signal flexible distribution system and method Robert P. Masleid 2010-02-09
7592836 Multi-write memory circuit with multiple data inputs Robert P. Masleid 2009-09-22
7495466 Triple latch flip flop system and method Robert P. Masleid 2009-02-24
7405597 Advanced repeater with duty cycle adjustment 2008-07-29
7375556 Advanced repeater utilizing signal distribution delay Robert P. Masleid 2008-05-20
6108745 Fast and compact address bit routing scheme that supports various DRAM bank sizes and multiple interleaving schemes Anurag Gupta 2000-08-22