Issued Patents All Time
Showing 251–275 of 329 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6369426 | Transistor with integrated photodetector for conductivity modulation | David L. Whitney | 2002-04-09 |
| 6331794 | Phase leg with depletion-mode device | — | 2001-12-18 |
| 6316336 | Method for forming buried layers with top-side contacts and the resulting structure | — | 2001-11-13 |
| 6291845 | Fully-dielectric-isolated FET technology | — | 2001-09-18 |
| 6272050 | Method and apparatus for providing an embedded flash-EEPROM technology | James A. Cunningham | 2001-08-07 |
| 6239752 | Semiconductor chip package that is also an antenna | — | 2001-05-29 |
| 6225662 | Semiconductor structure with heavily doped buried breakdown region | — | 2001-05-01 |
| 6215170 | Structure for single conductor acting as ground and capacitor plate electrode using reduced area | Pierangelo Confalonieri | 2001-04-10 |
| 6198114 | Field effect transistor having dielectrically isolated sources and drains and method for making same | — | 2001-03-06 |
| 6069385 | Trench MOS-gated device | — | 2000-05-30 |
| 6064109 | Ballast resistance for producing varied emitter current flow along the emitter's injecting edge | William P. Imhauser | 2000-05-16 |
| 6046473 | Structure and process for reducing the on-resistance of MOS-gated power devices | — | 2000-04-04 |
| 6011298 | High voltage termination with buried field-shaping region | — | 2000-01-04 |
| 5985721 | Single feature size MOS technology power device | Ferruccio Frisina, Angelo Magri, Giuseppe Ferla | 1999-11-16 |
| 5981998 | Single feature size MOS technology power device | Ferruccio Frisina, Angelo Magri', Giuseppe Ferla | 1999-11-09 |
| 5981318 | Fully-dielectric-isolated FET technology | — | 1999-11-09 |
| 5960277 | Method of making a merged device with aligned trench FET and buried emitter patterns | — | 1999-09-28 |
| 5897355 | Method of manufacturing insulated gate semiconductor device to improve ruggedness | Constantin Bulucea | 1999-04-27 |
| 5869371 | Structure and process for reducing the on-resistance of mos-gated power devices | — | 1999-02-09 |
| 5856696 | Field effect transistor having dielectrically isolated sources and drains | — | 1999-01-05 |
| 5821136 | Inverted field-effect device with polycrystalline silicon/germanium channel | Tsiu C. Chan, Yu-Pin Han, Elmer H. Guritz | 1998-10-13 |
| 5801396 | Inverted field-effect device with polycrystalline silicon/germanium channel | Tsiu C. Chan, Yu-Pin Han, Elmer H. Guritz | 1998-09-01 |
| 5798549 | Conductive layer overlaid self-aligned MOS-gated semiconductor devices | — | 1998-08-25 |
| 5773328 | Method of making a fully-dielectric-isolated fet | — | 1998-06-30 |
| 5756386 | Method of making trench MOS-gated device with a minimum number of masks | — | 1998-05-26 |