Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11094562 | Semiconductor device and method of manufacture | Leung Chi Ho, Shun Tik Yeung | 2021-08-17 |
| 10825757 | Semiconductor device and method with clip arrangement in IC package | Haibo Fan, Tim Boettcher, Wai Wong Chow | 2020-11-03 |
| 10658274 | Electronic device | Tim Boettcher, Haibo Fan, Wai Wong Chow, Shun Tik Yeung, Chi Ho Leung | 2020-05-19 |
| 10529644 | Semiconductor device | Shun Tik Yeung, Hans-Juergen Funke, Chi Ho Leung, Wolfgang Schnitt, Zhihao Pan | 2020-01-07 |
| 10410941 | Wafer level semiconductor device with wettable flanks | Chi Ho Leung, Shun Tik Yeung, Kan Wae Lam | 2019-09-10 |
| 10304759 | Electronic device and method of making same | Kan Wae Lam, Shun Tik Yeung, Chi Ho Leung, Chi Ling Shum | 2019-05-28 |
| 10262926 | Reversible semiconductor die | Kan Wae Lam, Harrie Horstink, Sven Walczyk, Chi Ho Leung, Thierry Jans +1 more | 2019-04-16 |
| 10256168 | Semiconductor device and lead frame therefor | Shun Tik Yeung, Chi Ho Leung, Kan Wae Lam, Hans-Juergen Funke, Shu-ming Yip | 2019-04-09 |
| 9947632 | Semiconductor device and method of making a semiconductor device | Chi Ho Leung, Shun Tik Yeung, Wai (Kan Wae) Lam | 2018-04-17 |
| 9640463 | Built-up lead frame package and method of making thereof | Kan Wae Lam, Chi Ho Leung, Shun Tik Yeung, Chi Ling Shum | 2017-05-02 |
| 9425130 | Package with multiple I/O side-solderable terminals | Chi Ho Leung, Wai Hung William Hor, Soenke Habenicht, WaiKeung Ho, Yee Wai Fung | 2016-08-23 |
| 9391007 | Built-up lead frame QFN and DFN packages and method of making thereof | Shun Tik Yeung, Chi Ho Leung, Kan Wae Lam, Chi Ling Shum | 2016-07-12 |
| 8809121 | Singulation of IC packages | Martin Li, Max Leung | 2014-08-19 |