Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10622262 | High performance SiGe heterojunction bipolar transistors built on thin film silicon-on-insulator substrates for radio frequency applications | Paul D. Hurwitz, Marco Racanelli, David J. Howard | 2020-04-14 |
| 10529836 | SiGe heterojunction bipolar transistor with crystalline raised base on germanium etch stop layer | — | 2020-01-07 |
| 10469035 | Amplifier using parallel high-speed and low-speed transistors | Jie Zheng, Samir Chaudhry | 2019-11-05 |
| 10347625 | Linearity and lateral isolation in a BiCMOS process through counter-doping of epitaxial silicon region | Kurt A. Moen, Paul D. Hurwitz | 2019-07-09 |
| 10325907 | Substrate isolation for low-loss radio frequency (RF) circuits | Kurt A. Moen, Paul D. Hurwitz | 2019-06-18 |
| 10319716 | Substrate isolation for low-loss radio frequency (RF) circuits | Kurt A. Moen, Paul D. Hurwitz | 2019-06-11 |
| 10297591 | BiCMOS integration using a shared SiGe layer | Todd Thibeault | 2019-05-21 |
| 10290631 | Linearity and lateral isolation in a BiCMOS process through counter-doping of epitaxial silicon region | Kurt A. Moen, Paul D. Hurwitz | 2019-05-14 |
| 10290630 | BiCMOS integration with reduced masking steps | Todd Thibeault | 2019-05-14 |
| 10243523 | Ultra-broadband transimpedance amplifiers (tia) for optical fiber communications | Payam Heydari, Seyed Mohammad Hossein Mohammadnezhad, Alireza Karimi Bidhendi, Michael Green, David J. Howard | 2019-03-26 |
| 10177044 | Bulk CMOS RF switch with reduced parasitic capacitance | Marco Racanelli, Paul D. Hurwitz | 2019-01-08 |
| 10177045 | Bulk CMOS RF switch with reduced parasitic capacitance | Marco Racanelli, Paul D. Hurwitz | 2019-01-08 |
| 10068997 | SiGe heterojunction bipolar transistor with crystalline raised base on germanium etch stop layer | — | 2018-09-04 |
| 9941353 | Structure and method for mitigating substrate parasitics in bulk high resistivity substrate technology | Paul D. Hurwitz, Marco Racanelli | 2018-04-10 |
| 9673081 | Isolated through silicon via and isolated deep silicon via having total or partial isolation | Hadi Jebory, David J. Howard, Marco Racanelli | 2017-06-06 |
| 9673191 | Efficient fabrication of BiCMOS devices | Todd Thibeault | 2017-06-06 |
| 9640528 | Low-cost complementary BiCMOS integration scheme | Todd Thibeault | 2017-05-02 |
| 9577035 | Isolated through silicon vias in RF technologies | Paul D. Hurwitz, Hadi Jebory | 2017-02-21 |
| 9436092 | Semiconductor fabrication utilizing grating and trim masks | George Talor, David J. Howard | 2016-09-06 |
| 9209264 | Heterojunction bipolar transistor having a germanium raised extrinsic base | David J. Howard, George Talor, Gerson R. Ortuno | 2015-12-08 |
| 9064886 | Heterojunction bipolar transistor having a germanium extrinsic base utilizing a sacrificial emitter post | David J. Howard, George Talor, Gerson R. Ortuno | 2015-06-23 |
| 7968417 | Method for integrating high voltage and high speed bipolar transistors on a substrate and related structure | — | 2011-06-28 |