Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11121851 | Differential sensing circuit for clock skew calibration relative to reference clock | Manu Basil, Mohan Yang, Roland Nii Ofei Ribeiro | 2021-09-14 |
| 10892742 | Duty-cycle calibration based on differential clock sensing | Roland Nii Ofei Ribeiro, Horia Giuroiu | 2021-01-12 |
| 8928398 | Differential analog signal processing stage with reduced even order harmonic distortion | Bumha Lee | 2015-01-06 |
| 8588289 | Adaptive signal equalizer with segmented coarse and fine controls | Amit Rane, Nicolas Nodenot, Laurence D. Lewicki, Benjamin Buchanan | 2013-11-19 |
| 8325791 | System and method for providing adaptively equalized data signal with alternately adjusted data signal boost and sliced data signal amplitude | Amit Rane, Nicolas Nodenot, Laurence D. Lewicki, Benjamin Buchanan | 2012-12-04 |
| 8270463 | System and method for adaptively equalizing data signals with higher and lower data rates | Amit Rane, Nicolas Nodenot, Laurence D. Lewicki, Benjamin Buchanan | 2012-09-18 |
| 7994807 | Built-in test circuit for testing AC transfer characteristic of high-speed analog circuit | Babak Matinpour, Vijaya Ceekala | 2011-08-09 |
| 7902013 | Method of forming a semiconductor die with reduced RF attenuation | Jeffrey A. Babcock | 2011-03-08 |
| 7649409 | All-pass termination network with equalization and wide common-mode range | Babak Matinpour, Vijaya Ceekala, Ramsin M. Ziazadeh | 2010-01-19 |
| 7598575 | Semiconductor die with reduced RF attenuation | Jeffrey A. Babcock | 2009-10-06 |
| 7395286 | Method for generating non-overlapping N-phases of divide-by-N clocks with precise 1/N duty ratio using a shift register | Jitendra Mohan | 2008-07-01 |
| 7256651 | System and method for providing a constant swing high-gain complementary differential limiting amplifier | Ramsin M. Ziazadeh | 2007-08-14 |
| 7209007 | Combined analog signal gain controller and equalizer | Abu-Hena Mostafa Kamal, Jitendra Mohan | 2007-04-24 |
| 7086788 | Optical sub-assembly for opto-electronic modules | William Paul Mazotti, Peter Deane, Luu Thanh Nguyen, Ken Pham, Bruce Carlton Roberts +6 more | 2006-08-08 |
| 6970048 | Inductive-capacitive (LC) based quadrature voltage controlled oscillator (VCO) with deterministic quadrature signal phase relationship | Varadarajan Devnath, Jitendra Mohan, Quyet Nguyen | 2005-11-29 |
| 6950490 | Fault state detection mechanism for a ring-counter-based frequency divider-by-N that generates non-overlapping N-phases of divide-by-N clocks with 1/N duty ratio | Jitendra Mohan | 2005-09-27 |
| 6916121 | Optical sub-assembly for optoelectronic modules | William Paul Mazotti, Peter Deane, Luu Thanh Nguyen, Ken Pham, Bruce Carlton Roberts +6 more | 2005-07-12 |
| 6320422 | Complementary source coupled logic | — | 2001-11-20 |