NN

Nicolas Nodenot

NS National Semiconductor: 8 patents #229 of 2,238Top 15%
MH Macom Technology Solutions Holdings: 3 patents #66 of 265Top 25%
ML Mindspeed Technologies, Llc.: 1 patents #97 of 197Top 50%
📍 Mountain View, CA: #1,825 of 11,022 inventorsTop 20%
🗺 California: #50,852 of 386,348 inventorsTop 15%
Overall (All Time): #410,483 of 4,157,543Top 10%
12
Patents All Time

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDate
11444813 Method and apparatus for CTLE equalizer adaptation based on samples from error slicers Jian Wang 2022-09-13
11146340 Complementary data flow for noise reduction 2021-10-12
11139949 Equalizer adaptation based on eye monitor measurements Yohan Piccin 2021-10-05
8934598 Integrated video equalizer and jitter cleaner Atul Gupta, Ryan Latchman 2015-01-13
8588289 Adaptive signal equalizer with segmented coarse and fine controls Amit Rane, Yongseon Koh, Laurence D. Lewicki, Benjamin Buchanan 2013-11-19
8325791 System and method for providing adaptively equalized data signal with alternately adjusted data signal boost and sliced data signal amplitude Amit Rane, Yongseon Koh, Laurence D. Lewicki, Benjamin Buchanan 2012-12-04
8270463 System and method for adaptively equalizing data signals with higher and lower data rates Amit Rane, Yongseon Koh, Laurence D. Lewicki, Benjamin Buchanan 2012-09-18
7778323 System and method for providing a parameterized analog feedback loop for continuous time adaptive equalization incorporating low frequency attenuation gain compensation Laurence D. Lewicki 2010-08-17
7571360 System and method for providing a clock and data recovery circuit with a fast bit error rate self test capability Laurence D. Lewicki, Amjad T. Obeidat 2009-08-04
7555091 System and method for providing a clock and data recovery circuit with a self test capability Laurence D. Lewicki, Amjad T. Obeidat 2009-06-30
7404090 Device and computer system for power management using serial link connections Laurence D. Lewicki 2008-07-22
7233173 System and method for providing a low jitter data receiver for serial links with a regulated single ended phase interpolator Laurence D. Lewicki, Amjad T. Obeidat 2007-06-19